1. Field of the Invention
The present invention relates to a delay locked loop (DLL) circuit, and more particularly, to a DLL circuit that can operate at high speeds while reducing power consumption.
2. Description of the Related Art
A DLL circuit is included in a semiconductor memory device to perform phase adjustment so that an internal clock signal input to or output from the DLL circuit can be synchronized with an external clock signal. A DLL performs signal synchronization by delaying a signal input to or output from the DLL according to an external clock signal via a delay line.
FIG. 1 is a circuit diagram of a conventional delay locked loop (DLL) circuit 100. Referring to FIG. 1, the DLL circuit 100 includes a delay line 101, a duty cycle correction (DCC) circuit 120, a phase detection and control circuit 130, and a replica delay path 135.
The phase detection and control circuit 130 compares the phase of an external clock signal Ext_CLK with that of a corrected clock signal CCLK, and detects the phase difference between the external clock signal Ext_CLK and the corrected clock signal CCLK based on the phase of the external clock signal Ext_CLK. Then the phase detection and control circuit 130 transmits information regarding the detected phase difference to the phase mixer 150 so that the external clock signal Ext_CLK can be delayed by the detected phase difference in the phase mixer 150.
The delay line 101 generates an internal clock signal Int_CLK by delaying the external clock signal Ext_CLK for a predetermined amount of time, in response to the output of the phase detection and control circuit 130. The delay line 101 includes a delay circuit 110 and a phase mixer 150.
The delay circuit 110 includes a plurality of delay cells 114, 116, . . . , 118, and generates a plurality of clock signals D_0 through D_n by delaying the external clock signal Ext_CLK input to the delay circuit 110 at regular intervals. Whenever the external clock signal Ext_CLK passes through one delay cell, e.g., the delay cell 114, the external clock signal Ext_CLK is delayed for a time t1 and then is output to the phase mixer 150. The delay circuit 110 can further include a buffer 112 in front of the delay cells 114, 116, . . . , 118. Thus, the original external clock signal Ext_CLK that is not delayed is output to the phase mixer 150 as a first delayed signal D_0, and the result of delaying the external clock signal Ext_CLK by a time t1 is output to the phase mixer 150 as a second delayed signal D_1. If n delay cells are included, a signal generated by delaying the original external clock signal Ext_CLK by a time t1×n is output to the phase mixer 150 as an nth delayed signal D_n.
The phase mixer 150 receives the delayed signals D_0 through D_n from the delay circuit 110 and then selects one of the delayed signals D_0 through D_n, for example, a delayed signal D_i, and outputs the delayed signal D_i as the internal clock signal Int_CLK. The phase mixer 150 can be a multiplexer.
The DCC circuit 120 cancels and corrects a duty cycle error present in each received internal clock signal Int_CLK and then outputs a corrected clock signal CCLK whose duty cycle is maintained at a normal level (in general, a signal having a duty ratio of 50%:50%. The DCC circuit 120 includes an amplification unit 122, a charge pump 124, and a digital-to-analog converter (DAC) 126.
The amplification unit 122 adjusts the duty cycle of the internal clock signal Int_CLK in response to a control signal VC output from the charge pump 124.
The charge pump 124 adjusts the voltage of the control signal VC in response to the corrected clock signal CCLK received via the replica delay path 135.
The DAC 126 is installed in order to prevent duty cycle information from being erased in a power down mode of a memory device, such as a dynamic random access memory (DRAM). In the power down mode of a DRAM, power supply to the DCC circuit 120 is discontinued. If power supply is discontinued, a self-refresh operation of a memory cell is stopped and thus information stored in the memory cell is likely to be erased due to discharge of a capacitor. Thus the DAC 126 transforms the duty cycle information memorized in a voltage format into a digital signal and then stores the digital signal in order to prevent the duty cycle information from being erased. That is, the duty cycle information is latched in order to memorize it.
The replica delay path 135 compensates for a delay occurring in a first path PATH1 via which the corrected clock signal CCLK is transmitted from a first node N1 to a destination circuit (not shown) that actually uses the corrected clock signal CCLK. The internal clock signal CCLK adjusted by the DLL circuit 100 for signal synchronization is delayed again during movement to the destination circuit that actually uses the internal clock signal CCLK. Thus, the replica delay, path 135 is included in order to compensate for the delay in the first path PATH1. The phase of a delayed corrected clock signal CCLK_D is the same as that of a clock signal CLK_out transmitted to the destination circuit. The replica delay path 135 includes a plurality of delay cells (not shown) causing a delay equivalent to the delay occurring in the first path PATH1.
In the case of the conventional DLL circuit 100, the external clock signal Ext_CLK is first transmitted to the phase detection and control circuit 130. The phase detection and control circuit 130 compares the phases of the external clock signal Ext_CLK and the fed back delayed corrected clock signal CCLK_D and the phase difference therebetween. Information regarding the detected phase difference is transmitted to the phase mixer 150 in the delay line 101. The delay line 101 adjusts a rough delay, i.e., it performs coarse locking, according to the received information regarding the phase difference. Through rough delay adjustment (first delay), the internal clock signal Int_CLK approximates the external clock signal Ext_CLK.
If the internal clock signal Int_CLK on which coarse locking has been performed passes through the DCC circuit 120, the duty cycle of the internal clock signal Int_CLK is corrected and then output as the corrected clock signal CCLK. The corrected clock signal CCLK passing through the replica delay path 135 is delayed for the delay time in the first path path1. The phase detection and control circuit 130 compares the delayed corrected clock signal CCLK_D with the original external clock signal Ext_CLK and detects a fine delay time (second delay). Information regarding the detected fine delay time (second delay) is transmitted to the phase mixer 150. The phase mixer 150 precisely delays the external clock signal Ext_CLK for the detected fine delay time (second delay) and outputs a precisely adjusted internal clock signal Int_CLK.
The precisely adjusted internal clock signal Int_CLK is delayed by the replica delay path 135 and then is fed back to the phase detection and control circuit 130. The phase detection and control circuit 130 compares the internal clock signal Int_CLK that was precisely adjusted and delayed with an external clock signal. If the internal clock signal Int_CLK coincides with the external clock signal, the delay line 101 discontinues signal delay.
FIG. 2 is a circuit diagram illustrating the conventional delay cells 114, 116, 118 illustrated in FIG. 1. Referring to FIG. 2, each of the conventional delay cells 114, 116, . . . , 118 includes an even-numbered plurality of inverters 201 connected in series. The original signal input to the delay cells 114, 116, 118 is delayed while passing through the chain of two or even-numbered inverters 201 connected in series in each of the conventional delay cells 114, 116, . . . , 118, and then is output. The conventional delay cells 114, 116, . . . , 118, being inverter chain-type delay cells, have an advantage of consuming less power than other type delay cells, e.g., differential amplifier type delay cells. The type of the conventional delay cells 114, 116, . . . , 118 is not limited. For example, the conventional delay cells 114, 116, . . . , 118 can be delay cells (not shown) using differential amplifiers.
A conventional DLL performs coarse locking and fine locking by using delay cells, such as the delay cells 114, 116, . . . , 118.
However, all n delayed signals D_1 through D_n that are respectively output from the conventional delay cells 114, 116, . . . , 118 are supplied to the phase mixer 150 of FIG. 1. Here, n is a large value that is precisely determined according to a maximum signal delay time. Thus, the more complex the relationship among signals that are input to and output from the phase mixer 150, the greater the signal loading is.
Accordingly, in the case of the conventional DLL circuit 100 illustrated in FIG. 1 that uses inverter type delay cells, power consumption can be reduced but signal loading is increased. Also, the signal mixing performance of the phase mixer 150 is degraded, thus increasing jitter in a plurality of delayed signals D_i. Also, the inverter type delay cells are greatly influenced by signal change caused by variation in power, voltage, and temperature (PVT) variables.
In general, the faster a DRAM operates, the greater the jitter. However, a DRAM operating at high speeds must have a small jitter value in order to precisely transmit data. Thus the extent of jitter must be reduced.
A delay cell using differential amplifiers is constructed by connecting differential amplifiers in series and thus can effectively combat jitter and can robustly withstand variation in the PVT variables. Accordingly, a delay cell using differential amplifiers can be used instead of the inverter type delay cell that has a delay jitter problem and is significantly affected by variation in the PVT variables.
However, the differential amplifier type delay cell consumes a large amount of power. Also, since the relationship among signals that are input to and output from the delay cell is complex, the signal loading on the delay cell is increased. Accordingly, the high-speed operation of a semiconductor device, such as a DRAM, is limited.